SymPLFIED: Symbolic Program-Level Fault Injection and Error Detection Framework
نویسندگان
چکیده
منابع مشابه
Symbolic Fault Injection
Computer systems that are dependable in the presence of faults are increasingly in demand. Among available fault tolerance mechanisms, software-implemented hardware fault tolerance (SIHFT) is constantly gaining in popularity, because of its cost efficiency and flexibility. Fault tolerance mechanisms are often validated using fault injection, comprising a variety of techniques for introducing fa...
متن کاملError Detection with Directed Symbolic
In practice due to entailed memory limitations the most important problem in model checking is state space explosion. Therefore, to prove the correctness of a given design binary decision diagrams (BDDs) are widely used as a concise and symbolic state space representation. Nevertheless, BDDs are not able to avoid an exponential blow-up in general. If we restrict ourselves to nd an error of a de...
متن کاملArchitectural-Level Fault Simulation Using Symbolic Data
Architectural-level circuit information has been utilized in hierarchical test generation and design for testability in recent years. Analysis at a high level makes a complete gate-level description of the circuit under test unnecessary. In this paper, we propose a new fault simulation technique which uses architectural-level information. This approach allows us to simulate stuck-at faults in s...
متن کاملFault-tolerant quantum error detection
Quantum computers will eventually reach a size at which quantum error correction becomes imperative. Quantum information can be protected from qubit imperfections and flawed control operations by encoding a single logical qubit in multiple physical qubits. This redundancy allows the extraction of error syndromes and the subsequent detection or correction of errors without destroying the logical...
متن کاملLogic Bug Detection and Localization Using Symbolic Quick Error Detection
We present Symbolic Quick Error Detection (Symbolic QED), a structured approach for logic bug detection and localization which can be used both during pre-silicon design verification as well as post-silicon validation and debug. This new methodology leverages prior work on Quick Error Detection (QED) which has been demonstrated to drastically reduce the latency, in terms of the number of clock ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IEEE Transactions on Computers
سال: 2013
ISSN: 0018-9340
DOI: 10.1109/tc.2012.219